Field of the Invention
The disclosure relates generally to a delay cell in a standard cell library, and more particularly it relates to a delay cell in a standard cell library with low-power and low-variation.
Description of the Related Art
A large integrated circuit, such as an Application Specific Integrated Circuit (ASIC), generally includes a number of logic elements and sub-elements in a hierarchical arrangement. The circuitry is driven by clock pulses that are applied through an input clock and distributed via interconnect wiring to the various elements of the circuit.
In order for the circuit to function properly, the clock pulses must arrive at each clocked circuit element at the same time. However, the lengths of the wiring that conduct the clock pulses to the different blocks will generally be different. Since the length of time required for an electrical signal to propagate through a wire is proportional to the length of the wire, the clock pulses will arrive at the blocks at different times.
In addition, clock signal paths often include multiple levels of logic elements and buffering. Skew results if there are unequal numbers of elements in the signal paths or if there are variations in how long it takes a signal to pass through various elements. How long it takes a signal to pass through an element depends upon several factors, including the propagation delay characteristics of the particular element, the number of loads the element is driving, and the temperature of the element. Any variation of these factors between two signal paths will skew the clock signals. Even if these factors are identical, there may be variations between individual elements of the same type.
There are several reasons for attempting to eliminate skew. First, it limits the speed at which a system can run. Within a computer, tasks are often performed serially, with data being passed from one stage of the computer to another on subsequent clock cycles. The time period of the clock must be long enough to account for the time it takes a stage to process the data and propagate it to the next stage. Similarly, clock skew may prevent a system from being slowed down. It is often desirable to slow down a system clock for diagnostic purposes, but if slowed down too much, the system may no longer function.
It is clear that there exists a long and unfilled need for a technique capable of reducing clock skew while eliminating the shortcomings discussed above. The present invention solves these problems and provides circuit designers with a simple and inexpensive circuit for reducing integrated circuit clock skew.